As is well known, a processor executes a stream of instructions which can perform many different operations. A nop (no-operation) is an instruction that does nothing, that is it has no effect on any state of the processor.
On a traditional superscalar CPU, the nop instruction is used to pad out code (for alignment issues) or to provide a single cycle delay for timing critical operations. So-called VLIW (very long instruction word) machines operate by encoding a plurality of instructions in a single word. The machines are most effective when all instructions in a word can be processed in parallel in a single clock cycle. However, it is often not possible to write code in a suitable way to achieve this. Take a simple example, where a multiply instruction might take three cycles to complete, which means that there will be at least two clock cycles after the multiply instruction has been issued where the result of the multiply instruction is unavailable. During this time it is expected that other instructions will be executed which do not rely on the result of the multiply instruction being available. However, in some cases there is no other useful work to perform while waiting for the multiply instruction to be completed. In such an event, a nop instruction is used to provide a delay until the result of the multiply instruction becomes available. Instructions of different types can have different latencies (cycle time to completion), which can lead to a much higher proportion of nop instructions than in traditional processors.
One undesirable side effect of an increased number of nop instructions is an increase in the size of the program, as compared to the program which would be used by a traditional CPU. Conventionally each nop instruction has a bit length equivalent to that of an operative instruction. Larger programs can be undesirable as they take up more space in memory. Also, as most processors fetch their program via a cache system, an increase in program size can also result in an increase in the number of cache misses. Cache misses take up execution time and bus bandwidth and therefore the additional nop instructions can slow down the program or otherwise have an adverse effect on the system.
It is an aim of the present invention to deal with no-operation instructions in a manner which does not undesirably increase the size of the program.